View SNP-OP-BOARD-01_7601282.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

bcd.0 00 12_a i o ct - 24 - 2013 1 www.power - one.com data sheet the pfe1100 - 12 - 054xa is an 1100 watt ac to dc power - factor - corrected (pfc) power supply that converts standard ac mains power into a main output of 12 vdc for powering intermediate bus archite c- tures (iba) in high performance and reliability servers, routers, and network switch es. the pfe1100 - 12 - 054xa meets international safet y standards and displays the ce - mark for the european low voltage directive (lvd). o high performance servers o routers o switches pfe1100 - 12 - 054xa ? best - in - class, 80 plus certified platinum efficiency ? wide input voltage range: 90 - 264 vac ? ac input with power factor correction ? always - on 16.5 w programmable standby output (3.3/5 v) ? hot - plug capable ? parallel operation with active digital current sharing ? full digital controls for improved performance ? high density design: 25.6 w/in3 ? small form factor: 54.5 x 40.0 x 321.5 mm ? i2c communication interface for control, programming and monitoring with psmi and pmbus? protocol ? overtemperature, output overvoltage and overcurrent protection ? 256 bytes of eeprom for user information ? 2 status leds: ac ok and dc ok with fault signalling features description applications
pfe1100 - 12 - 054xa 2 www.power - one.com data sheet 1 ordering information pfe 1100 - 12 - 054 x a product family pfe front - ends power level 1100 w dash v1 output 12 v dash width 54 mm airflow n: normal r: reversed input a: ac 2 overview the pfe1100 - 12 - 054xa ac/dc power supply is a fully dsp controlled, highly efficient front - end power supply. it incorp o- rates resonance - soft - switching technology and interleaved power trains to reduce component stresses, providing increased system reliabilit y and very high efficiency. with a wide input operational voltage range and minimal linear derating of output power with input volta ge and temperature, the pfe1100 - 12 - 054xa maximizes power availability in demanding server, ne t- work, and other high availabil ity applications. the supply is fan cooled and ideally suited for integration with a matching ai r- flow paths. the pfc stage is digitally controlled using a state - of - the - art digital signal processing algorithm to guarantee best efficiency and unity power fac tor over a wide operating range. the dc/dc stage uses soft switching resonant techniques in conjunction with synchronous rectification. an active or - ing device on the output ensures no reverse load current and renders the supply ideally suited for operatio n in redundant power systems. the always - on standby output, with selectable voltage level (3.3/5.0 volts), provides power to external power distribution and management controllers. it is protected with an active or - ing device for maximum reliability. statu s information is provided with front - panel leds. in addition, the power supply can be controlled and the fan speed set via the i 2 c bus. the i 2 c bus allows full monitoring of the supply, including input and output voltage, current, power, and inside tempera tures. cooling is managed by a fan controlled by the dsp controller. the fan speed is adjusted automatically depending on the actual power demand and supply temperature and can be overridden through the i 2 c bus. figure 1 - pfe1100 - 12 - 054xa block diagram 3 absolute maximum ratings stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long - term reliabi l- ity, and cause permanent damage to the supply. parameter description / condition min nom max unit vi maxc max imum i nput continuous 264 va c l o g i c s i g n a l s v 1 s e n s e + l b u c k a u x c o n v e r t e r v s b s e n s e + v s b s e n s e - g n d v 1 v s b n p f c d c d c d i g i t a l p r i m c o n t r o l s v 1 s e n s e - i 2 c p w m f i l t e r p e p w m c o m m u n i c a t i o n b u s a p s d i g i t a l s e c c o n t r o l s e e p r o m f a n
bcd.0 00 12_a i o ct - 24 - 2013 3 www.power - one.com data sheet 4 input general condition: t a = 0 45 c unless otherwise noted. parameter description / condition min nom max unit v i nom nominal input v oltage 100 230 230 vac v i input voltage r anges normal operating ( v i min to v i max ) 90 264 vac v i red derated input v olt age r ange see figure 20 and figure 41 90 180 vac i i max max input c urrent 13 a rms i i p inrush current limitation v i min to v i max , t ntc = 25c ( figure 5 ) 40 a p f i input f requency 47 50/60 64 hz pf power factor v i nom , 50hz, > 0.3 i 1 nom 0.96 w/va v i on turn - on input v oltage 1) ramping up 80 87 vac v i off turn - off input v oltage 1) ramping down 75 85 vac efficiency without f an v i nom , 0.1? i x nom , v x nom , t a = 25c 90.3 % v i nom , 0.2? i x nom , v x nom , t a = 25c 93.4 v i nom , 0.5? i x nom , v x nom , t a = 25c 94.5 v i nom , i x nom , v x nom , t a = 25c 93.8 t hold hold - up time after last ac zero point, v 1 > 10.8v, v sb within regul a- tion, v i = 230vac, p x nom 12 ms 1) the front - end is provided with a minimum hysteresis of 3v during turn - on and turn - off within the ranges. 4.1 input fuse quick - acting 16 a input fuses (5 x 20 mm) in series with both the l - and n - line inside the power supply protect against s e- vere defects. the fuses are not accessible from the outside and are therefore not serviceable parts. 4.2 inrush current the ac - dc power supply exhibits a n x - capacitance of only 3.2f, resulting in a low and short peak current, when the supply is connected to the mains. the internal bulk capacitor will be charged through an ntc which will limit the inrush current. note: do not repeat plug - in / out operations within a short time, or else the internal in - rush current limiting device (ntc) may not sufficiently cool down and excessive inrush current or c omponent failure(s) may result. 4.3 input under - voltage if the sinusoidal input voltage stays below the input undervoltage lockout threshold vi on, the supply will be inhibited. once the input voltage returns within the normal operating range, the supply will return to normal operation again. 4.4 power factor corre ction power factor correction (pfc) is achieved by controlling the input current waveform synchronously with the input voltage. a fully digital controller is implemented giving outstanding pfc results over a wide input voltage and load ranges. the input cu rrent will follow the shape of the input voltage. if for instance the input voltage has a trapezoidal waveform, then the curr ent will also show a trapezoidal waveform. in addition, the pfc circuit has a stability region to be observed when operating the po wer supply at high input current ampl i- tudes. at a low source inductance (<150h) the power supply will work stable up to its full maximum input current (13 arms). if the source inductance is higher, the region with stable pfc operation is slightly reduced (as shown in figure 4 ) . the power supply will also work in the unstable region, but it may exhibit a slight current oscillation during the sinusoidal p eak. 4.5 efficiency high efficiency (see figure 2 ) is achieved by using state - of - the - art silicon power devices in conjunction with soft - transition topologies minimizing switching losses and a full digital control scheme. synchronous rectifie rs on the output reduce the losses in the high current output path. the speed of the fan is digitally controlled to keep all components at an optimal ope r- a t ing temperature regardless of the ambient temperature and load condi tions.
pfe1100 - 12 - 054xa 4 www.power - one.com data sheet figure 2 - efficiency vs. l oad current (ratio metric loading) figure 3 - power factor vs. l oad current figure 4 - pfc s tability region figure 5 - inrush current, v in = 230vac, 90 ch4 : v in (200v/div), ch3 : i in (20a/div) 5 output general condition: t a = 0 +45 c unless otherwise noted. parameter description / condition min nom max unit main output v 1 v 1 nom nominal output v oltage 0.5 ? i 1 nom , t amb = 25 c 12.0 vdc v 1 set output setpoint a ccuracy - 0.5 +0.5 % v 1 nom d v 1 tot total r egulation v i min to v i max , 0 to 100% i 1 nom , t a min to t a max - 1 +1 % v 1 nom p 1 nom nominal output p ower v 1 = 12 vdc 1080 w i 1 nom nominal output c urrent v 1 = 12 vdc 90.0 adc v 1 pp output ripple voltage v 1 nom , i 1 nom , 20mhz bw (see section 5 .1) 150 mvpp d v 1 load load regulation v i = v i nom , 0 - 100 % i 1 nom 60 mv d v 1 line line regulation v i =v i min v i max 0 mv i 1 max current limitation pfe1100 - 12 - 054na v i > 115 vac, t a < 45c v i > 90 vac, t a < 45c v i > 180 vac, t a < 45c v i > 90 vac, t a < 45c 93.5 74 100 78 adc current l imitation pfe1100 - 12 - 054ra 91 71 95 75 d i share current sharing deviation from i 1 tot / n, i 1 > 10% - 3 +3 a d v dyn dynamic load regulation i 1 = 50% i 1 nom , i 1 = 5 100% i 1 nom , d i 1 /d t = 1a/s, recovery within 1% of v 1 nom - 0.6 0.6 v t rec recovery time 1 ms t ac v1 start - up t ime from ac v 1 = 10.8 vdc (see figure 7 ) 2 sec t v1 rise rise time v 1 = 1090% v 1 nom (see figure 8 ) 1 10 ms c load capacitive loading t a = 25c 30000 f 88 89 90 91 92 93 94 95 0 200 400 600 800 1000 po [w] efficiency [%] vi = 230vac, fan internal vi = 230vac, fan external platinum 0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96 0.98 1 0 200 400 600 800 1000 po [w] power factor vi = 230vac vi = 115vac 0 2 4 6 8 10 12 14 16 0 100 200 300 400 500 600 700 800 900 1000 line inductance [uh] input current [arms] stable unstable
bcd.0 00 12_a i o ct - 24 - 2013 5 www.power - one.com data sheet parameter description / condition min nom max unit standby output v sb v sb nom nominal output voltage 0.5 ? i sb nom , t amb = 25c vsb_sel = 1 3.3 vdc v sb set output setpoint accuracy vsb_sel = 0 5.0 vdc vsb_sel = 0 / 1 - 0.5 +0.5 % v 1nom d v sb tot total r egulation v i min to v i max , 0 to 100% i sb nom , t a min to t a max - 1 +1 % v sb nom p sb nom nominal output power v sb = 3.3 vdc , normal airflow 16.5 w v sb = 3.3 vdc , reverse airflow 11.5 v sb = 5.0 vdc, normal/reverse airflow 16.5 i sb nom nominal output current v sb = 3.3 vdc, normal airflow 5 adc v sb = 3.3 vdc, reverse airflow 3.5 v sb = 5.0 vdc, normal/reverse airflow 3.3 v sb pp output r ipple v oltage v sb nom , i sb nom , 20 mhz bw (see section 5 .1) 1 0 0 mvpp d v sb droop 0 - 100 % i sb nom vsb_sel = 1 67 mv vsb_sel = 0 44 i sb max current limitation vsb_sel = 1, normal airflow 5.25 6 adc vsb_sel = 1, reverse airflow 4 4.75 vsb_sel = 0, normal/reverse airflow 3.45 4.3 d v sb dyn dynamic load regulation i sb = 50% i sb nom , i sb = 5 100% i sb nom , d i o /d t = 0.5 a/s, recovery within 1% of v 1 nom - 3 3 % v sbnom t rec recovery time 250 s t ac vsb start - up time from ac v sb = 90% v sb nom (see figure 7 ) 2 sec t vsb rise rise time v sb = 1090% v sb nom (see figure 8 ) 4 20 ms c load capacitive loading t amb = 25c 10000 f 5.1 output voltage ripple internal capacitance at the 12 v output (behind the or - ing circuitry) is minimized to prevent disturbances during hot plug. in order to provide low output ripple voltage in the application, external capacitors should be added close to the power supply output. the setup of figure 6 has been used to evaluate suitable capacitor types . the capacitor combinations of table 1 and table 2 should be used to reduce the output ripple voltage. the ripple voltage is measured with 20 mhz bwl, close to the external capacitors. figure 6 - output ripple test setup note: care must be taken when using ceramic capacitors with a total capacitance of 1 f to 50 f on output v 1 , due to their high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects. table 1 - suitable capacitors for v 1 external capacitor v1 dv1max unit 2pcs 47f/16v/x5r/1210 150 mvpp 1pcs 1000f/16v/low esr aluminum/?10x20 150 mvpp 1pcs 270f/16v/conductive polymer/?8x12 120 mvpp 2pcs 47f/16v/x5r/1210 plus 1pcs 270f conductive polymer or 1pcs 1000f low esr alcap 60 mvpp table 2 - suitable capacitors for v sb external capacitor vsb dv1max unit 1pcs 10f/16 v/x5r/1206 100 mvpp 2pcs 10f/1v/x5r/1206 60 mvpp 1pcs 47f/16v/x5r/1210 50 mvpp 2pcs 100/6.3v/x5r/1206 35 mvpp v 1 p g n d v s b p f e x x x x - 1 2 - 0 5 4 n a c o n n e c t i o n b o a r d
pfe1100 - 12 - 054xa 6 www.power - one.com data sheet the output ripple voltage on v sb is influenced by the main output v 1 . evaluating v sb output ripple must be done when max i- mum load is applied to v 1 . figure 7 - turn - on ac line 230vac, full load (200ms/div) ch1 : v 1 (2v/div) ch2 : v sb (2v/div ) ch3 : vin (200v/div) figure 8 - turn - on ac line 230vac, full load (5ms/div) ch1 : v 1 (2v/div) ch2 : v sb (2v/div) ch3 : vin (200v/div) figure 9 - turn - off ac line 230vac, full load (20ms/div) ch1 : v 1 (2v/div) ch2 : v sb (2v/div) ch3 : vin (200v/div) figure 10 - short circuit on v1 (500 s/div) ch1 : v 1 (2v/div) ch2 : v sb (1v/div) ch3 : i 1 (200a/div) figure 11 - short circuit on v1 (50ms/div) ch1 : v 1 (2 v/div) ch2 : v sb (1v/div) ch3 : i 1 (200a/div) figure 12 - ac drop out 10ms (10ms/div) ch1 : v 1 (2v/div) ch2 : v sb (1v/div) ch4 : v in (200v/div) figure 13 - ac drop out 20ms (10ms/div) ch1: v 1 (5v/div) ch2 : v sb (2 v/div) ch4 : v in (200v/div) figure 14 - ac drop out 20ms (200ms/div), v 1 restart after 1s ch1 : v 1 (5 v/div) ch2 : v sb (2 v/div) ch4 : i 1 (200v/div)
bcd.0 00 12_a i o ct - 24 - 2013 7 www.power - one.com data sheet figure 15 - load transient v 1 , 5 to 50a (500 s/div) ch2 : v 1 (200mv/div) ch4 : i 1 (20a/div) figure 16 - load transient v 1 , 50 to 5a (500 s/div) ch2 : v 1 (200mv/div) ch4 : i 1 (20a/div) figure 17 7 - load transient v 1 , 40 to 85a (500 s/div) ch2 : v 1 (200mv/div) ch4 : i 1 (20a/div) figure 18 - load transient v 1 , 85 to 40a (500 s/div) ch2 : v 1 (200mv/div) ch4 : i 1 (20a/div) 6 protection parameter description / condition min nom max unit f input fuses ( l + n ) not user accessible, quick - acting (f) 16 a v 1 ov ov threshold v 1 13.3 14.5 vdc t ov v1 ov latch off time v 1 1 ms v sb ov ov threshold v sb 115 125 % v sb t ov vsb ov latch off time v sb 1 ms i v1 lim current limit v 1 pfe1100 - 12 - 054na v i > 115vac, t a < 45c v i > 90vac, t a < 45c 93.5 74 100 78 a current limit v 1 pfe1100 - 12 - 054ra v i > 180vac, t a < 45c v i > 90vac, t a < 45c 92 72 100 78 i v1 sc max short circuit current v 1 v 1 < 3v 110 a t v1 sc short circuit regulation time v 1 < 3v, time until i v1 is limited to < i v1 sc 2 ms t v1 sc off short circuit latch off time time to latch off when in short circuit 200 ms t sd over temperature on heat sinks automatic shut - down 115 c 6.1 overvoltage protection the pfe front - ends provide a fixed threshold overvoltage (ov) protection implemented with a hw comparator. once an ov condition has been triggered, the supply will shut down and latch the fault condition. the latch can be unlocked by disco n- necting the supply from the ac mains or by toggling the pson_l input.
pfe1100 - 12 - 054xa 8 www.power - one.com data sheet 6.2 vsb undervoltage detection both main and standby outputs are mo nitored. led and pwok_h pin signal if the output voltage exceeds 5% of its nom i- nal voltage. output undervoltage protection is provided on the standby output only. when v sb falls below 75% of its nominal voltage, the main output v 1 is inhibited. 6.3 current li mitation main output the main output exhibits a substantially rectangular output characteristic controlled by a software feedback loop. if it runs in current limitation and its voltage drops below ~10.0 vdc for more than 200 ms, the output will latch off (standby remains on). figure 19 - current limitation on v 1 (v i = 230vac) a second current limitation circuit on v 1 will immediately switch off the main output if the output current increases beyond the peak current trip point. t he supply will re - start 4 ms later with a soft start, if the short circuit persists ( v 1 < 10.0v for >200 ms) the output will latch off; otherwise it continuous to operate (hardware current limit triggers). the latch can be unlocked by disconnecting the supply from the ac mains or by toggling the pson_l input. the main output current limitation will decrease if the ambient (inlet) temperature increases beyond 45c or if the ac input voltage is too low (see figure 20 and figure 21 ). note that the actual current limitation on v 1 will begin at a current level a p- proximately 4 a higher than what is shown in figure 20 . (s ee also chapter 9 temperature and fan control for additional information .) standby output the standby output exhibits a substantially rectangular output characteristic down to 0v (no hiccup mode / latch off). if it runs in current limitation and its output voltage drops below the uv threshold, then the main output will be inhibited (standby r e- mains on). the current limitation of the standby output is independent of the ac input voltage, but is derated with the ambie nt temperature (only for reverse airflow). figure 20 - derating on v 1 vs. v i and t a for pfe1100 - 12 - 054na figure 21 - derating on v 1 vs. v i and t a for pfe1100 - 12 - 054ra 0 2 4 6 8 10 12 0 20 40 60 80 100 main output current [a] main output voltage [v] 0 20 40 60 80 100 90 115 140 165 190 215 240 265 input ac voltage [vac] main output nominal current [a] ta < 35c ta < 45c ta < 55c ta < 65c 0 20 40 60 80 100 90 115 140 165 190 215 240 265 input ac voltage [vac] main output nominal current [a] ta < 35c ta < 45c ta < 55c ta < 65c
bcd.0 00 12_a i o ct - 24 - 2013 9 www.power - one.com data sheet figure 22 - current limitation on v sb figure 23 - temperature derating on v sb 7 monitoring parameter description / condition min nom max unit v i mon input rms v oltage v i min v i v i max - 2.5 +2.5 % i i mon input rms c urrent i i > 4 a rms - 5 +5 % i i 4 a rms - 0.2 +0.2 a rms p i mon true input p ower p i > 100 w - 5 +5 % p i 100 w - 5 +5 w v 1 mon v 1 v oltage - 2 +2 % i 1 mon v 1 c urrent i1 > 10 a - 2 +2 % i1 10 a - 0.2 +0.2 a p o nom total output p ower po > 120 w - 4 +4 % po 120 w - 4.5 +4.5 w v sb mon standby v oltage - 0.1 +0.1 v i sb mon standby c urrent i sb i sb nom - 0.2 +0.2 a 8 signaling and control 8.1 electrical characteristics parameter description / condition min nom max unit pskill_h / pson_l / vsb_sel / hotstandbyen_h i nputs v il input low level voltage - 0.2 0.8 v v ih input high level voltage 2.4 3.5 v i il, h maximum input sink o r source current 0 1 ma r pupskill_h internal pull up resistor o n pskill _ h 100 k r pupson_l internal pull up resistor o n pson _ l 10 k r puvsb_sel internal pull up resistor o n vsb _ sel 10 k r puhotstandbyen_h internal pull up resistor o n hotstandbyen _ h 10 k r low resistance pin t o sgnd f or low level 0 1 k r high resistance pin t o sgnd f or high level 50 k pwok_h o utput v ol output low level voltage i sink < 4 ma 0 0.4 v v oh output high level voltage i source < 0.5 ma 2.6 3.5 v r pupwok_h internal pull up resistor o n pwok _ h 1 k acok_h o utput 0 1 2 3 4 5 0 2 4 6 8 standby output current [a] standby output voltage [v] vsb=3.3v vsb=5v 0 1 2 3 4 5 6 0 10 20 30 40 50 60 70 ambient temperature [c] standby output nominal current [a] vsb = 3.3v, ra vsb = 3.3v, na vsb = 5v, na & ra
pfe1100 - 12 - 054xa 10 www.power - one.com data sheet v ol output low level voltage i sink < 2 ma 0 0.4 v v oh output high level voltage i source < 50 a 2.6 3.5 v r puacok_h internal pull up resistor o n acok _ h 10 k smb_alert_l o utput v ext maximum external pull up voltage 12 v v ol output low level voltage i source < 4 ma 0 0.4 v i oh maximum high level leakage current 10 a r pusmb_alert_l internal pull up resistor o n smb _ alert _ l none k 8.2 interfacing with signals all signal pins have protection diodes implemented to protect internal circuits. when the power supply is not powered, the protection devices start clamping at signal pin voltages exceeding 0.5 v. therefore all input signals should be driven only by an open collector/drain to prevent back feeding inputs when the power supply is switched off. if interconnec ting of signal pins of several power supplies is required, then this should be done by decoupling with small si g- nal schottky diodes as shown in examples in figure 24 (except for smb_alert_l, ishare and i 2 c pins). this will ensure the pin voltage is not affected by an unpowered power supply. smb_alert_l pins can be interconnected without decoupling diodes, since these pins have no internal pull up resistor and use a 15 v zener diode as protection device against positive voltage on pins. ishare pins must be interconnected without any additional components. this in - /output also has a 15 v zener diode as a pro tection device and is disconnected from internal circuits when the power supply is switched off. figure 24 - interconnection of s ignal p ins 8.3 front led s the front - end has 2 front leds showing the status of the supply. led number one is green and indicates ac power is on or off, while led number two is bi - colored: green and yellow, and indicates dc power presence or fault situations. for the pos i- tion of the leds see table 3 lists the different led status. table 3 - led st a tus operating condition led signaling ac led ac line within range solid green ac line uv condition off dc led 1) pson_l high blinking yellow (1:1) hot - standby mode blinking yellow/green (1:2) v 1 or v sb out of regulation solid yellow over temperature shutdown output over voltage shutdown ( v 1 or v sb ) output over current shutdown ( v 1 or v sb ) fan error (>15%) over temperature warning blinking yellow/green (2:1) minor fan regulation error (>5%, <15%) blinking yellow/green (1:1) 1) the order of the criteria in the table corresponds to the testing precedence in the controller. p s u 1 p d u p s u 2 v s b _ s e l p s u 1 p d u p s u 2 3 . 3 v v s b _ s e l 3 . 3 v 3 . 3 v p w o k 3 . 3 v p w o k
bcd.0 00 12_a i o ct - 24 - 2013 11 www.power - one.com data sheet 8.4 present_l this signaling pin is recessed within the connector and will contact only once all other connector contacts are closed. this active - low pin is used to indicate to a power distribution unit controller that a supply is plugged in. the maximum curren t on present_l pin should not exceed 10 ma. figure 25 - present_l signal pin 8.5 pskill_h input the pskill_h input is active - high and is located on a recessed pin on the connector and is used to disconnect the main output as soon as the power supply is being plugged out. this pin should be connected to sgnd in the power distribution unit. the standby output will remain on regardless of the pskill_h input state. 8.6 ac turn - on / drop - outs / acok_h the power supply will automatically turn - o n when connected to the ac line under the condition that the pson_l signal is pulled low and the ac line is within range. the acok_h signal is active - high. the timing diagram is shown in figure 26 and referenced in table 4 . table 4 - ac turn - on / dip timing operating condition min max unit t ac vsb ac line to 90% v vsb 2 sec t ac v1 ac line to 90% v 1 2 sec t acok_h on1 acok_h signal on delay (start - up) 2000 ms t acok_h on2 acok_h signal on delay (dips) 100 ms t acok_h off acok_h signal off delay 5 ms t vsb v1 del v sb to v 1 delay 10 500 ms t v1 holdup effective v 1 holdup time 12 ms t vsb holdup effective v sb holdup time 20 ms t acok_h v1 acok_h to v 1 holdup 7 ms t acok_h vsb acok_h to v sb holdup 15 ms t v1 off minimum v 1 off time 1000 1200 ms t vsb off minimum v sb off time 1000 1200 ms figure 26 - ac turn - on timing figure 27 - ac short dips figure 28 - ac long dips v 1 v s b 0 v p r e s e n t _ l p f e p d u a c i n p u t v s b v 1 p s o n _ l a c o k _ h p w o k _ h t a c v s b t v s b r i s e t v 1 r i s e t a c v 1 t p w o k _ h d e l t a c o k _ h o n 1 t v s b v 1 d e l a c i n p u t v s b v 1 p s o n _ l a c o k _ h p w o k _ h t v 1 h o l d u p t a c o k _ h o f f t v 1 o f f t p w o k _ h w a r n t a c o k _ h o n 2 a c i n p u t v s b v 1 p s o n _ l a c o k _ h p w o k _ h t v s b h o l d u p t a c o k _ h v s b t a c o k _ h o f f t v 1 h o l d u p t a c o k _ h v 1 t v 1 o f f t v s b o f f t p w o k _ h w a r n
pfe1100 - 12 - 054xa 12 www.power - one.com data sheet 8.7 pson_l input the pson_l is an internally pulled - up (3.3 v) input signal to enable/ disable the main output v 1 of the front - end. this active - low pin is also used to clear any latched fault condition. the timing diagram is given in figure 29 and the pa rameters in table 5 . table 5 - pson_l timing operating condition min max unit t pson_l v1on pson_l to v 1 delay (on) 2 20 ms t pson_l v1off pson_l to v 1 delay (off) 2 20 ms t pson_l h min pson_l minimum high time 10 ms 8.8 pwok_h signal the pwok_h is an open drain output with an internal pull - up to 3.3 v indicating whether both v sb and v 1 outputs are within regulation. this pin is active - low. the timing diagram is shown in figure 26 / figure 29 and referenced in the table 6 . figure 29 - pson_l turn - on/off timing table 6 - pwok_h timing operating condition min max unit t pwok_h del pwok_h to v 1 delay (on) 100 500 ms t pwok_h warn *) pwok_h to v 1 delay (off) caused by: pskill_h 0 1 ms pson_l, acok_h, ot, fan failure 1 2.5 ms uv and ov on vsb 1 30 ms oc on v1 (software trigger) - 11 0 ms oc on v1 (hardware trigger) - 1 0 ms ov on v1 - 3 0 ms *) a positive value means a warning time, a negative value a delay (after fact). 8.9 current share the pfe front - ends have an active current share scheme implemented for v 1 . all the ishare current share pins need to be interconnected in order to activate the sharing function. if a supply has an internal fault or is not turned on, it will disc onnect its ishare pin from the share bus. this will prevent dragging the output down (or up) in such cases. the current share function uses a digital bi - directional data exchange on a recessive bus configuration to transmit and r e- ceive current share information. the controller implements a master/slave current share function. the power supply provi d- ing t he largest current among the group is automatically the master. the other supplies will operate as slaves and increase their output current to a value close to the master by slightly increasing their output voltage. the voltage increase is limi ted to +250 mv. the standby output uses a passive current share method (droop output voltage characteristic). 8.10 sense inputs both main and standby outputs have sense lines implemented to compensate for voltage drop on load wires. the maximum allowed voltage drop is 200 mv on the positive rail and 100 mv on the pgnd rail. with open sense inputs the main output voltage will rise by 270 mv and the standby output by 50 mv. therefore if not used, these inputs should be connected to the power output and pgnd close to the powe r supply connector. the sense inputs are protected against short circuit. in this case the power supply will shut down. 8.11 hot - standby operation the hot - standby operation is an operating mode allowing to further increase efficiency at light load conditions in a redundant power supply system. under specific conditions one of the power supplies is allowed to disable its dc/dc stage. this will save the power losses associated with this power supply and at the same time the other power supply will operate in a loa d range having a better efficiency. in order to enable the hot standby operation, the hotstandbyen_h and the ishare pins need to be inter connected. a power supply will only be allowed to enter the hot - standby mode, when the ho t- standbyen_h pin is high, the load current is low (see figure 30 ) and the supply was allowed to enter the hot - standby mode by the system controller via the appropriate i 2 c command (by default disabled). the system controller needs to ensure that only one of the power supplies is allowed to enter the hot - standby mode. v s b a c i n p u t v 1 p s o n _ l a c o k _ h p w o k _ h t p s o n _ l v 1 o n t v 1 r i s e t p w o k _ h d e l t p s o n _ l v 1 o f f t p w o k _ h w a r n t p s o n _ l h m i n
bcd.0 00 12_a i o ct - 24 - 2013 13 www.power - one.com data sheet if a power supply is in a fault condition, it will pull low its active - high hotstandbyen_h pin which indicates to th e other power supply that it is not allowed to enter the hot - standby mode or that it needs to return to normal operation should it a l- ready have been in the hot - standby mode. note : the system controller needs to ensure that only one of the power supplies is allowed to en ter the hot - standby model. figure 31 shows the achievable power loss savings when using the hot - standby mode operation. a total power loss redu c- tion of 45% is achievable. figure 30 - hot - standby enable/disable current thresholds figure 31 - psu power losses with/without hot - standby mode figure 32 - recommended hot - standby configuration in order to prevent voltage dips when the active power supply is unplugged while the other is in hot - standby mode, it is strongly recommended to add the external circuit as shown in figure 32 . if the present_l pin status needs also to be read by the system controller, it is recommended to exchange the bipolar transistors with small signal mos transistors or with digital transistor s. 8.12 i 2 c / smbus communication the interface driver in the pfe supply is referenced to the v 1 return. the pfe supply is a communication slave device only; it never initiates messages on the i 2 c/smbus by itself. the communication bus vo ltage and timing is defined in table 7 fu r- ther characterized through: ? there are no internal pull - up resistors ? the sda/scl ios are 3.3/5 v tolerant ? full smbus clock speed of 100 kbps ? clock stretching limited to 1 ms ? scl low time - out of >25 ms with recovery within 10 ms ? recognizes any time start/stop bus conditions figure 33 - physical layer of communication interface the smb_alert_l signal indicates that the power supply is experiencing a problem that the system agent should invest i- gate. this is a logical or of the shutdown and warning events. the power supply responds to a read command on the ge n- eral smb_alert_l call address 25(0x19) by sending its status register. 1 p s u o n 2 p s u o n 4 5 a 3 6 a 9 0 a t o t a l s y s t e m c u r r e n t 0 10 20 30 40 50 60 0 100 200 300 400 500 600 700 800 po [w] total power loss [w] hot-standby disabled hot-standby enabled p s u 1 p s u 2 v s b c s h o t s t a n d b y e n p r e s e n t _ l v s b c s h o t s t a n d b y e n p r e s e n t _ l 3 x 3 k 3 3 . 3 / 5 v r p u l l - u p t x r x s d a / s c l
pfe1100 - 12 - 054xa 14 www.power - one.com data sheet communication to the dsp or the eeprom will be possible as long as the input ac voltage is provided. if no ac is present, communication to the unit is possible as long as it is connected to a life v 1 output (provided e.g. by the redundant unit). if only v sb is provided, communication is not possible. table 7 - i 2 c / smbus specification parameter description condition min max unit v il input low voltage - 0.5 1.0 v v ih input high voltage 2.3 5.5 v v hys input hysteresis 0.15 v v ol output low voltage 3 ma sink current 0 0.4 v t r rise time for sda and scl 20+0.1c b 1 300 ns t of output fall time vihmin ? vilmax 10 pf < c b 1 < 400 pf 20+0.1c b 1 250 ns i i input current scl/sda 0.1 vdd < vi < 0.9 vdd - 10 10 a c i internal capacitance for each scl/sda 5 0 pf f scl scl clock frequency 0 100 khz r pu external pull - up resistor f scl 100 khz 1000 ns / c b 1 ? t hdsta hold time (repeated) start f scl 100 khz 4.0 s t low low period of the scl clock f scl 100 khz 4.7 s t high high period of the scl clock f scl 100 khz 4.0 s t susta setup time for a repeated start f scl 100 khz 4.7 s t hddat data hold time f scl 100 khz 0 3.45 s t sudat data setup time f scl 100 khz 250 ns t susto setup time for stop condition f scl 100 khz 4.0 s t buf bus free time between stop and start f scl 100 khz 5 m s 1 cb = capacitance of bus line in pf, typically in the range of 10400 pf figure 34 - i 2 c / smbus timing 8.13 address/protocol selection (aps) the aps pin provides the possibility to select the communication protocol and address by connecting a resistor to v 1 return (0 v). a fixed addressing offset exists between the controller and the eeprom. note - if the aps pin is left open, the supply will operate with the psmi protocol at controller / eeprom addresses 0xb6 / 0xa6. - the asp pin is only read at start - up of the power supply. therefore it is not possible to change the communication protocol and address dynamically. t r t l o w t h i g h t l o w t h d s t a t s u s t a t h d d a t t s u d a t t s u s t o t b u f t o f s d a s c l
bcd.0 00 12_a i o ct - 24 - 2013 15 www.power - one.com data sheet table 8 - address and protocol encoding r aps () 1) protocol i2c address 2) controller eeprom 820 pmbus? 0xb0 0xa0 2700 0xb2 0xa2 5600 0xb4 0xa4 8200 0xb6 0xa6 15000 psmi 0xb0 0xa0 27000 0xb2 0xa2 56000 0xb4 0xa4 180000 0xb6 0xa6 1) e12 resistor values, use max 5% resistors, see also figure 35. 2) the lsb of the address byte is the r/w bit. figure 35 - i 2 c address and protocol setting 8.14 controller and eeprom access the controller and the eeprom in the power supply share the same i 2 c bus physical layer (see figure 36 ) . an i 2 c driver device assures logic level shifting (3.3/5 v) and a glitch - free clock stretching. the driver also pulls t he sda/scl line to nearly 0 v when driven low by the dsp or the eeprom providing maximum flexibility when additional external bus repeaters are needed. such repeaters usually encode the low state with different voltage levels depending on the transmission direction. the dsp will automatically set the i 2 c address of the eeprom with the necessary offset when its own address is changed / set. in order to write to the eeprom, first the write protection needs to be disabled by sending the appropriate command to the dsp. by default the write protection is on. the eeprom provides 256 bytes of user memory. none of the bytes are used for the operation of the power supply. figure 36 - i 2 c bus to dsp and eeprom 8.15 eeprom protocol the eeprom follows the industry communication protocols used for this type of device. even though page write / read commands are defined, it is recommended to use the single byte write / read commands. write the write command follows the smbus 1.1 write byte protocol. after the device address with the write bit cleared a first byte with the data address to write to is sent followed by the data byte and the stop condition. a new start condition on the bus should only occur after 5ms of the last stop condition t o allow the eeprom to write the data into its memory. read the read command follows the smbus 1.1 read byte protocol. after the device address with the write bit cleared the data address byte is sent followed by a repeated start, the device address and t he read bit set. the eeprom will respond with the data byte at the specified location. a d c a p s r a p s 3 . 3 v 1 2 k d s p e e p r o m d r i v e r s d a s c l a p s w p a d d r s c l i s d a i p r o t e c t i o n a d d r e s s & p r o t o c o l s e l e c t i o n s a d d r e s s w a d a t a a d d r e s s a d a t a a p d a t a n a p s a d d r e s s w a d a t a a d d r e s s a s a d d r e s s r a
pfe1100 - 12 - 054xa 16 www.power - one.com data sheet 8.16 psmi protocol new power management features in computer systems require the system to communicate with the power supply to access current, voltage, fan speed, and temp erature information. current measurements provide data to the system for determining potential system configuration limitations and provide actual system power consumption for facility planning. temperature and fan monitoring allow the system to better man age fan speeds and temperatures for optimizing system acoustics. voltage monitoring allows the system to calculate input wattage and warning of system voltage regulation problems. the power su p- ply management interface (psmi) supports diagnostic capabilitie s and allows managing of redundant power supplies. the communication method is smbus. the current design guideline is version 2.12. the communication protocol is register based and defines a read and write communication protocol to read / write to a single register address. all registers are accessed via the same basic command given below. no pec (packet error code) is used. write the write protocol used is the smbus 2.0 write word protocol. all writes are 16 - bit words; byte reads are not supported nor allo wed. the shaded areas in the figure indicate bits and bytes written by the psmi master device. see pfe programming manual for further information. read the read protocol used is the smbus 2.0 read word protocol. all reads are 16 - bit words; byte reads are not supported nor allowed. the shaded areas in the figure indicate bits and bytes written by the psmi master device. see pfe programming manual for further information. 8.17 pmbus? protocol the power management bus (pmbus?) is an open standard protocol that defines means of communicating with power conversion and other devices. for more information, please see the system management interface forum web site at : www.powersig.org . pmbus? command codes are not register addresses. they describe a specific command to be executed. the pfe1100 - 12 - 054xa supply supports the following basic command structures: ? clock stretching limited to 1 ms ? scl low time - out of >25 ms with recovery within 10 ms ? recognized any time start/stop bus conditions write the write protocol is the smbus 1.1 write byte/word protocol. note that the write protocol may end after the command byte or after the first data byte (byte command) or then after sending 2 data bytes (word command). in addition, block write commands are supported with a total maximum length of 255 bytes. see pfe programming manual for further information. s a d d r e s s w a r e g i s t e r i d a d a t a l o w b y t e a d a t a h i g h b y t e a p s a d d r e s s w a r e g i s t e r i d a d a t a l o w b y t e a s a d d r e s s r a d a t a h i g h b y t e n a p s a d d r e s s w a c o m m a n d a d a t a l o w b y t e 1 ) a d a t a h i g h b y t e 1 ) a p 1 ) o p t i o n a l s a d d r e s s w a c o m m a n d a b y t e 1 a b y t e n a p b y t e c o u n t a
bcd.0 00 12_a i o ct - 24 - 2013 17 www.power - one.com data sheet read the read protocol is the smbus 1.1 read byte/word proto col. note that the read protocol may request a single byte or word. in addition, block read commands are supported with a total maximum length of 255 bytes. see pfe programming manual bca.00006 for further information. 8.18 graphical user interface power - one provides with its power - one i 2 c utility a windows? xp/vista/win7 compatible graphical user interface allowing the programming and monitoring of the pfe1100 - 12 - 054xa front - end. t he utility can be downloaded on: www.power - one.com and supports both the psmi and pmbus? protocols. the gui allows automatic discovery of the units connected to the communication bus and will show them in the navigation tree. in the monitoring view t he power supply can be controlled and monitored. if the gui is used in conjunction with the snp - op - board - 01 evaluation kit it is also possible to control the pson_l pin(s) of the power supply. further there is a button to disable the internal fan for appro ximately 10 seconds. this allows the user to take input power measurements without fan consumptions to check efficiency compliance to the climate saver computing platinum specific a- tion. the monitoring screen also allows to enable the hot - standby mode on th e power supply. the mode status is monitored and by changing the load current it can be monitored when the power supply is being disabled for further energy savings. this obviously requires 2 power supplies being operated as a redundant system (as in the e valuation kit). note: the user of the gui needs to ensure that only one of the power supplies have the hot - standby mode enabled. figure 37 - monitoring dialog of the i 2 c utility s a d d r e s s w a c o m m a n d a d a t a ( l o w ) b y t e a s a d d r e s s r a d a t a h i g h b y t e 1 ) n a p 1 ) o p t i o n a l s a d d r e s s w a c o m m a n d a b y t e 1 a s a d d r e s s r a b y t e n n a p b y t e c o u n t a
pfe1100 - 12 - 054xa 18 www.power - one.com data sheet 9 temperature and fan control to achieve best cooling results sufficient airflow through the supply must be ensured. do not block or obstruct the airflow at the rear of the supply by placing large objects directly at the output connector. the pfe1100 - 12 - 054na is provided with a normal airflow, which m eans the air enters through the dc - output of the supply and leaves at the ac - inlet. the pfe1100 - 12 - 054ra is provided with a reverse airflow, which means the air enters through the ac - inlet of the supply and leaves at the dc - output. pfe supplies have been d esigned for horizontal operation. the fan inside of the supply is controlled by a microprocessor. the rpm of the fan is adjusted to ensure optimal supply coo l- ing and is a function of output power and the inlet temperature. for the normal airflow version ad ditional constraints apply because of the ac - connector. in a normal airflow unit, the hot air is exiting the power supply unit at the ac - inlet. the iec connector on the unit is rated 105 c . if 70 c mating connector is used then end user must derate the input power to meet a maximum 70 c temperature at the front, see figure 41 . note: it is the responsibility of the user to check the front temperature in such cases. the unit is not limiting its power aut o- matically to meet such a temperature limitation. figure 38 - airflow direction figure 39 - fan speed vs. main output load for pfe1100 - 12 - 054na figure 40 - fan speed vs. main output load for pfe1100 - 12 - 054ra figure 41 - thermal derating for pfe1100 - 12 - 054na figure 42 - thermal derating for pfe1100 - 12 - 054ra normal airflow normal ai rflow reverse airflow reverse airflow all rights strictly reserved. reproducti o n or issue to third parties in any form is not permitted without writ ten authorit y from po wer-one. d r a w in g n o . tit l e m a t e ria l fi ni s h di m . i n m m r e visi o n modifie d mech. eng. a pproved elec. e ng. app roved mfg. ap proved a3 >120-4 00: 0. 2 t o l e r a n c e s u n l e s s o t h e r w is e st a t e d : 0.5-30: 0.1 >30-12 0: 0.1 5 s u p e rs e d e s: 5 / 5 www.p ower-o ne.com issued s c a l e s iz e s h e e t wh 2009-0 9-17 wh 2009-1 1-10 - - - - - - snp fa m i ly prod uct g a sn p 1 1 0 0 -1 2 g _ ga 0 0 3 a l l m ate r i a l s used, and fini shed pro d uct, must m eet t h e requir ements of the curr ent r o h s dire cti v e 20 02 / 95 /ec. f or add i t i onal i n f orm at i on u s e oth er data f i l e s , o r a sk . 0 5 10 15 20 25 0 20 40 60 80 100 main output current [a] fan speed [1000xrpm] high line fan curve low line fan curve min speed at isb > 3a 0 5 10 15 20 25 0 20 40 60 80 100 main output current [a] fan speed [1000xrpm] high line fan curve low line fan curve min speed at isb > 3a 0 200 400 600 800 1000 0 10 20 30 40 50 60 ambient temperature [c] main output power [w] vi > 90vac vi > 103vac vi > 115vac vin = 90vac vin = 115vac 0 200 400 600 800 1000 0 10 20 30 40 50 60 ambient temperature [c] main output power [w] vi > 90vac vi > 145vac vi > 180vac
bcd.0 00 12_a i o ct - 24 - 2013 19 www.power - one.com data sheet 10 electromagnetic compatibility 10.1 immunity note: most of the immunity requirements are derived from en 55024:1998/a2:2003. parameter description / condition criterion esd contact discharge iec / en 61000 - 4 - 2, 8 kv, 25+25 discharges per test point (metallic case, leds, connector body) b esd air discharge iec / en 61000 - 4 - 2, 15 kv, 25+25 discharges per test point (non - metallic user accessible surfaces) b radiated electromagnetic field iec / en 61000 - 4 - 3, 10 v/m, 1 khz/80% amplitude modulation, 1 s pulse modulation, 10 khz2 ghz a burst iec / e n 61000 - 4 - 4, level 3 ac port 2 kv, 1 minute dc port 1 kv, 1 minute b surge iec / en 61000 - 4 - 5 line to earth: level 3, 2 kv line to line: level 2, 1 kv v sb : a, v 1 : b 1 a rf conducted immunity iec/en 61000 - 4 - 6, level 3, 10 vrms, cw, 0.1 80 mhz a voltage dips and interruptions iec/en 61000 - 4 - 11 1: vi 230 v, 100% load, phase 0 , dip 100%, duration 10 ms 2: vi 230 v, 100% load, phase 0 , dip 100%, duration 20 ms 3: vi 230 v, 100% load, phase 0 , dip 100%, duration >20 ms a v sb : a, v 1 : b v sb , v 1 : b 10.2 emission parameter description / condition criterion conducted emission en55022 / cispr 22: 0.15 30 mhz, qp and avg, single unit class a 6 db margin en55022 / cispr 22: 0.15 30 mhz, qp and avg, 2 units in rack system class a 6 db margin radiated emission en55022 / cispr 22: 30 mhz 1 ghz, qp, single unit class a 6 db margin en55022 / cispr 22: 30 mhz 1 ghz, qp, 2 units in rack system class a 6 db margin harmonic emissions iec61000 - 3 - 2, vin = 115 vac / 60 hz, & vin = 230vac/ 50 hz, 100% load class a acoustical noise 4 6 dba at 1 meter, 25c, 5 0% load - ac flicker iec61000 - 3 - 3 , vin = 2 30 vac / 60 hz, 100% load pass 11 safety / approvals maximum electric strength testing is performed in the factory according to iec/en 60950, and ul 60 950. input - to - output electric strength tests should not be repeated in the field. power - one will not honor any warranty claims resulting from ele c- tric stren gth field tests. parameter description / condition min nom max unit agency approvals ul 60950 - 1 second edition can/csa - c22.2 no. 60950 - 1 - 07 second edition iec 60950 - 1:2005 en 60950 - 1:2006 approved by independent body (see ce declaration) isolation strength input (l/n) to case (pe) basic input (l/n) to output reinforced output to case (pe) functional d c creepage / clearance primary (l/n) to protective earth (pe) according to safety standard mm primary to secondary electrical strength test input to case kvac input to output output and signals to case 1 v 1 drops to 90 97% v 1 nom for 3ms
pfe1100 - 12 - 054xa 20 www.power - one.com data sheet 12 environmental parameter description / condition min nom max unit t a ambient temperature v i min to v i max , i 1 nom , i sb nom 0 +45 c t aext extended temp . range derated output (see figure 20 and figure 41 ) +45 +65 c t s storage temperature non - operational - 20 +70 c altitude operational, above sea level - 10,000 feet n a audible noise v i nom , 50% i o nom , t a = 25c 42 dba 13 mechanical parameter description / condition min nom max unit dimensions width 54.5 mm height 40.0 depth 321.5 m weight 1.05 kg figure 43 - side view 1 figure 44 - top view figure 45 - side view 2 reverse air flow direction normal air flow direction note: a 3d step file of the power supply casing is available on request.
bcd.0 00 12_a i o ct - 24 - 2013 21 www.power - one.com data sheet figure 46 C front and rear view 14 connections power supply connector: tyco electronics p/n 2 - 1926736 - 3 ( note: column 5 is recessed (short pins)) mating connector : tyco electronics p/n 2 - 1926739 - 5 or fci 10108888 - r10253slf pin name description output 6, 7, 8, 9, 10 v1 +12 vdc main output 1, 2, 3, 4, 5 pgnd power ground (return) control pins a1 vsb standby positive output (+3.3/5 v) b1 vsb standby positive output (+3.3/5 v) c1 vsb standby positive output (+3.3/5 v) d1 vsb standby positive output (+3.3/5 v) e1 vsb standby positive output (+3.3/5 v) a2 sgnd signal ground (return) b2 sgnd signal ground (return) c2 hotstandbyen_h hot standby enable signal: active - high d2 vsb_sense_r standby output negative sense e2 vsb_sense standby output positive sense a3 aps i 2 c address and protocol selection (select by a pull down resistor) b3 n/c reserved c3 sda i 2 c data signal line d3 v1_sense_r main output negative sense e3 v1_sense main output positive sense a4 scl i 2 c clock signal line b4 pson_l power supply on input (connect to a2/b2 to turn unit on): active - low c4 smb_alert_l smb alert signal output: active - low d4 n/c reserved e4 acok_h ac input ok signal: active - high a5 pskill_h power supply kill (lagging pin): active - high b5 ishare current share bus (lagging pin) c5 pwok_h power ok signal output (lagging pin): active - high d5 vsb_sel standby voltage selection (lagging pin) e5 present_l power supply present (lagging pin): active - low ac led dc led
pfe1100 - 12 - 054xa 22 www.power - one.com data sheet 15 accessories item description ordering part number source power - one i 2 c utility windows xp/vista/7 compatible gui to program, control and monitor pfe front - ends (and other i 2 c units) n/a www.power - one.com dual connector board connector board to operate 2 pfe units in parallel. includes an on - board usb to i 2 c converter (use power - one i 2 c utility as desktop software). snp - op - board - 01 power - one latch lock optional latch lock to prevent acc i- dental removal of the power supply from the system while the ac plug is engaged. xsl.00019.0 power - one nuclear and medical applications - power - one products are not designed, intended for use in, or authorized for use as critical components in life support sy s- tems, equipment used in hazardous environments, or nuclear control systems without the express written consent of the respect ive divisional president of pow er - one, inc. technical revisions - the appearance of products, including safety agency certifications pictured on labels, may change depending on the date manuf actured. spec i- fications are subject to change without notice.

▲Up To Search▲

Price & Availability of SNP-OP-BOARD-01

	To Download SNP-OP-BOARD-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .